1. Field of the Invention
The present invention relates to an interrupt circuit and an interrupt processing method for microcomputers, and more particularly to an interrupt circuit for microcomputers which processes multiple interrupts while the CPU is processing a main program.
2. Description of the Prior Art
In general, a requirement for interrupt processing occurs frequently while a main program is being processed in a microcomputer. Particularly, two interrupt requests such as an external interrupt request and a timer interrupt request, frequently occur at one time.
A microcomputer has a plurality of interrupt programs to be processed during the processing of the main program. A plurality of interrupt request signals are given a priority level in order to cope with the case where a plurality of interrupt request signals for a plurality of interrupt programs arise at the same time. Specifically, the plurality of interrupt request signals are assigned to either a low priority or a high priority.
Conventionally, a program memory of the microcomputer is provided with a plurality of address areas (sometimes called vectors), and either a low priority level or high priority level is a priori assigned to the plurality of address areas by means of a hardware. The plurality of interrupt request signals are fixed to either a low priority level or a high priority level in accordance with specifications of the microcomputer.
Thus, specifications of some microcomputers require assignment of a high priority level to a software interrupt request signal, producing such a disadvantage in the prior art that if two interrupt request signals with a high priority and a low priority occur simultaneously with the software interrupt request signal assigned to a high priority level, a remaining part of the processing of the interrupt request signal given a high priority in response to the software interrupt request signal is consecutively carried out after a minimum required processing of the interrupt request signal with a high priority is firstly conducted without executing the processing of the interrupt signal with a low priority.
In order to overcome this drawback in the prior art, according to this invention, the software interrupt request signal is constantly assigned to a low priority level with the help of the program processing.
In the case where two interrupt requests arise concurrently while a main program is being processed, the conventional solution comprises the steps of:
performing the minimum required processing of an external interrupt;
suppressing the remaining external interrupt processing to carry out timer interrupt processing; and
completing the remaining processing of the external interrupt request by means of software interrupt processing initiated by a software interrupt request signal.
Software interrupt processing is used when executing the processing of two interrupt requests which occur simultaneously with high efficiency.
Further, in the solution set forth in the above, when the external interrupt processing and the timer interrupt processing occurred at the same time were executed, for instance, it was necessary to assign a low priority level to the external interrupt processing request signal for performing the external interrupt processing and a high priority to the timer interrupt request signal for performing the timer interrupt processing. As a result, a minimum required processing of the timer interrupt request signal with a high priority level is carried out and a software interrupt request signal is issued. Then, processing of the external interrupt request signal with a low priority level is performed. Finally, in response to the software interrupt request signal, a rest of the processing of the timer interrupt request signal is then executed, namely, the processing of the interrupt request signal with a high priority level is executed before processing the interrupt request signal with a low priority.
As described above, a software interrupt request signal was assigned to the same priority assignment data selector as an interrupt request signal given either a high or a low priority.
According to the prior art, when a software interrupt request signal is assigned to the same priority assignment data selector as an interrupt request signal with a high priority, the software interrupt processing is executed and the rest of the timer interrupt processing is executed subsequent to the software interrupt processing, because the software interrupt request signal is already fixed to a high priority. If the software interrupt request signal is assigned to a high priority, the software interrupt processing will be executed so as to execute before the external interrupt processing; however, it is essential to execute the minimum required processing of the timer interrupt request when the external and timer interrupt requests arise at the same time.
Thus, in the prior art, users could not always use the software interrupt request processing as they intend whenever multiple interrupt processings were required.